Electronics Overview
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UNDER CONSTRUCTION - NONE OF THIS IS GUARANTEED TO BE TRUE OR CORRECT!
Contents |
[edit] Introduction
The 8pi data acquisition system uses standard NIM-based analogue electronics to perform signal processing and then a mixture of CAMAC and FERA-based modules to digitize and correlate these signals for ultimate readout by a VME system running the MIDAS DAQ (http://midas.triumf.ca).
There are four detector subsystems to the 8pi;
- Germanium - Twenty Compton-suppressed coaxial High-purity Germanium detectors for detecting gamma rays.
- SCEPTAR - Twenty plastic scintillator paddles in the vacuum chamber for detecting beta particles. (Sometimes replaced by a single zero-degree scintillator.)
- DANTE - Ten Barium Fluoride (BaF2) scintillators for fast timing measurements of gamma-ray transitions.
- PACES - Five liquid-nitrogen cooled Lithium-drifted Silicon (Si(Li)) detectors for detecting Internal Conversion Electrons (ICE).
The electronics for each detector subsystem is handled separately in one of four separate datastreams. Each of the four datastreams runs almost independently of the other streams. The only place that the datastreams interact, ie. the signals are used together in the same modules, is in the determination of the master trigger and in the VME readout of the data. The electronics in each datastream is essentially identical. This means that if you understand one of the datastreams then you understand all the datastreams. This page will now continue with a description of the PACES datastream which should be translatable to understanding the other datastreams as well. The differences will come in the length of various gates because the responses of different detectors have different time constants (For example the DANTE signals are very quick).
The electronics are separated in 3 main stages. Each stage relies on input from the previous stage and cannot begin until those signals are presented.
- Stage 1: Generates and presents the energy and time signals to the FERA modules and generates the pretriggers for this stream
- Stage 2: Determination of the master trigger - This is common to all datastreams
- Stage 3: Enables and controls the readout of the FERA data and VME readout (This can only happen when a Si MT is issued)
In the following description various signal types are involved, NIM, ECL and TTL. These are simply different signal standards and refer to the polarity and amplitude of logic pulses. Often different electronics modules require their input to be one standard or the other. This necessitates the signals to be converted from one type to the other by various modules known as either; level convertors, level translators, ECL-NIM, NIM-ECL etc.
[edit] PACES: Energy and Time signals
The preamplifiers generate two output signals which are processed by either an Ortec 572A Spectroscopy Amplifier to produce an energy signal or by an Ortec 474 Timing Filter Amplifier (TFA) and Ortec 583B Constant Fraction Discriminator (CFD) to produce a timing signal. The energy signals are transported directly to the Analogue-to-Digital Convertor (ADC) FERA module for readout. The timing signal is essentially a logic pulse and is used as both the input data to the Time-to-Digital Convertor (TDC) FERA module, and as to generate the pretriggers for the Master Triggering logic.
[edit] PACES: Generation of Pretriggers
There are three pretriggers generated by the PACES stream; SI (Silicon Singles), SCSI (SCaled-Down Silicon Singles) and SISI (Silicon-Silicon Coincidence or Silicon Doubles). These pretriggers are used in the Master Triggering logic to determine whether the conditions of the master trigger have been met and whether a master trigger will be issued or not. The OR of the five timing signals is used to determine the SI pretrigger and the same signal is passed through a rate divider to generate the SCSI pretrigger. A Lecroy Majority Logic Unit (MALU) module is used to generate the SISI pretrigger. All five timing signals are presented to the MALU and the MDO signal (the SISI pretrigger) is only true if more than one SI has fired.
These pretriggers are used as input into the N18, Lecroy 2365 ULM module used in the Master Triggering Logic described in detail elsewhere and briefly below.
[edit] PACES: Master Triggering
The master triggering logic, described in more detail here, takes pretriggers from the four datastreams and checks for coincidences between them to satisfy whatever master trigger conditions have been set. If the conditions are met then a Master Trigger (MT) signal is issued to each datastream that is involved in the trigger. This MT is essential to enable the third stage of the electronics, which is the control of FERA and VME readout of data.
[edit] PACES: FERA Readout Control
This section of electronics generates a series of logic pulses which are time-ordered and vetoed appropriately in order to fully control the readout of the energy, timing and ULM signals of this stream. The setup ensures that the modules are told to convert and read out their signals in the correct order and that during readout the modules do not receive additional logic pulses which can cause confusion and crashes. The master trigger for the silicon stream produced by the master triggering logic modules (N21) initiates this series of signals.
| Logic Signal | Polarity | Started with | Ended with | Module | Purpose |
|---|---|---|---|---|---|
| Master Trigger | negative | Master Triggering Logic | shortly after start | Lecroy 2365 ULM (N21) | Initiates this series of logic signals |
| Master VETO Trigger | negative | Start of Master trigger | 1 microsecond after Last pass | Lecroy 222 G&D Generator | Used to prevent subsequent triggers during event processing |
| ADC GAI | Negative | Start of master trigger | Min. of 500ns after peak of energy pulse from spec. amp. | Lecroy 222 G&D Generator | External Gate for FERA driver module - initiates conversion of the ADCs and ULM. |
| TDC GAI | Negative | Start of master trigger | Should stop shortly after the end of the ADC pulse | Lecroy 222 G&D Generator | Common stop for TDCs. Also Latching signal for ULM clock |
| FIFO Gate | Negative | End of ADC GAI | Last Pass Signal OR end of dead time signal | Lecroy 222 G&D Generator | Prevents TDC GAI from stopping the readout of TDCs before all have been read out (Which can cause the modules to freeze) |
The following scope shots can aid in setting up and confirming the time ordering and duration of the logic pulses.
 Ge Gates. Ch1: Master Trigger, Ch2: Energy Signal, Ch3: ADC GAI, Ch4: FIFO |
 PACES Gates. Ch1: ADC GAI, Ch2: TDC GAI, Ch3: FIFO, Ch4: Last Pass |
 PACES Gates. Ch1: ADC GAI, Ch2: TDC GAI, Ch3: FIFO, Ch4: Last Pass |
[edit] PACES: FERA Chain
The energy and timing signals are digitized by CAMAC FERA modules and the signals passed to a VME FIFO module for readout. The logic signals which are passed within this chain are outlined in the diagram to the right. The FERA Driver facilitates the readout from each module in the FERA chain. The writing out each word has an associated set of handshake signals to ensure everything works correctly. The ADCs (Energies signals) read out first, followed by the TDC (Time signals) module and finally the ULM (ULM Times). When the FERA Driver receives the ADC GAI signal it passes this GATE to the modules. This initiates the conversion process in the modules which turns the analoge signal into a digital word. When each module has digitized their signal they generate a request (REQ) to the FERA Driver. Only one module can pass its data to the FERA Driver at a time. This is controlled by the Read Enable (REN) signal which is given to the first module in the chain, then passed to the second after the first has finished etc. The process is a bit like running a relay race where each runner (module) can only run their lap (read out data) when they have the baton (REN logic signal). When a module has the REN signal it will send a write strobe (WSK) signal to the FERA Driver and then the data word. When the Driver has successfully received the word it will send back a write acknowledge signal (WAK). This is the handshake. When all the modules have readout their data to the FERA driver a clear (CLR) signal is sent to all modules to empty their memory and prepare for the next event. All the data sent to the FERA Driver are held in a buffer memory in that module ready to be passed to the VME FIFO.
[edit] PACES: VME Readout
The data is passed to the MIDAS mserver through a VME First-In, First-Out (FIFO) module. The manual is here: http://daq-plone.triumf.ca/HR/VME/SiS/sis3700.pdf/at_download/file
